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multirate to 2.7 gb/s clock and data recovery ic with integrated limiting amp ADN2819 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features meets sonet r e quirements for jitter transfer/generation/tolerance quantizer sens itivity: 4 m v typical adjustable slic e level: 100 m v 1.9 gh z minim u m bandwidth patented clock recovery archit ecture loss of signal d e tect range: 3 mv to 15 m v single referenc e clock frequen c y for all r a tes, including 15/14 (7%) wra pper rate choice of 19.44 mhz, 3 8 .88 m hz, 77. 76 mh z, or 155.52 m hz refclk lvpecl/lvds/lvcmos/lvttl compatible inpu ts (lvpecl/lvds only at 15 5.52 mhz) 19.44 m hz osci llator on-chip to be used with external crysta l loss of lock indicator loopback mod e for high spee d test data output sque lch and bypass f eatures single-supply operation: 3.3 v low power: 540 mw t y pical 7 mm 7 mm 48-lea d lfcsp applic ati o ns sonet oc-3/-1 2 /-48, sd h st m-1/-4/-16, gbe and 1 5 /14 fec rates wdm transponders regenerators/repeaters test eq uipmen t backplane applications produc t d e scripti o n the ADN2819 p r o v ides the r e c e i v er f u n c tion s o f q u a n t i za tion, sig n a l le vel d e te c t , a nd clo c k and d a t a r e co ver y a t r a tes o f o c -3 , o c -12, o c -48, g i ga b i t e t h e r n et, a nd 15/14 fe c ra t e s. al l sonet j i t t e r r e q u ir em e n ts a r e m e t, incl uding j i t t e r t r a n sfer , ji t t er ge n e r a t i o n , a n d ji t t er t o lera n c e . a l l sp e c if ica t ion s a r e q u o t ed f o r C40c t o +85c am b i en t tem p era t ur e , unles s ot he r w i s e note d . the d e v i ce is i n tende d fo r wdm sy stem a p pli c a t ion s , an d ca n b e us e d wi t h ei t h er an ext e r n al r e fer e n c e clo c k o r a n o n -chi p os cil l a t o r wi t h ext e r n al cr ys tal . b o th na t i v e ra t e s a nd 15/14 ra t e dig i t a l wr a p p e rs a r e s u p p o r t e d b y th e ADN2819, wi t h o u t an y ch ange of re f e re nc e cl o c k . this d e vice, to get h er wi t h a pi n dio d e and a ti a p r e a m p lif i e r , ca n im p l em en t a h i ghl y in t e gra t ed , l o w cos t , l o w po w e r , f i be r opt i c re c e ive r . the r e cei v er f r o n t e nd sig n a l de te c t cir c ui t indi ca te s w h e n t h e in p u t sig n al le ve l has fal l en b e lo w a us er -ad j usta b l e thr e sh old . th e s i g n a l de te c t c i rc u i t h a s h y ste r e s i s to pre v e n t ch a tte r a t t h e output . the ADN2819 is a v a i la b l e in a c o m p ac t 7 mm 7 mm, 48-lead chi p s c a l e p a ckage. func tio n a l block di agram level detect da t a retiming divider 1/2/4/16 fra c tional divider freq uency lock detect or loop fil ter phase shifter phase det . vco xt al osc loop fil ter q u antizer /n ADN2819 slicep/ n v cc vee cf 1 c f2 lol refsel[0..1] refclkp/n xo1 xo2 refsel sel[0..2] clk outp/n d a t a outp/ n sdout thradj vref nin pin 2 2 2 2 2 3 02999-0-001 fi g u r e 1 .
ADN2819 rev. b | page 2 of 24 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 thermal characteristics .............................................................. 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 definition of terms.......................................................................... 9 maximum, minimum, and typical specifications ................... 9 input sensitivity and input overdrive....................................... 9 single-ended vs. differential ...................................................... 9 los response time ................................................................... 10 jitter specifications..................................................................... 10 theory of operation ...................................................................... 12 functional description .................................................................. 14 multirate clock and data recovery......................................... 14 limiting amplifier ..................................................................... 14 slice adjust .................................................................................. 14 loss of signal (los) detector .................................................. 14 reference clock.......................................................................... 14 lock detector operation .......................................................... 15 squelch mode ............................................................................. 16 test modes: bypass and loopback........................................... 16 applications information .............................................................. 17 pcb design guidelines ............................................................. 17 choosing ac-coupling capacitors ......................................... 19 dc-coupled application .......................................................... 20 lol toggling during loss of input data............................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 5/04data sheet changed from rev. a to rev. b updated format..............................................................universal changes to specifications ............................................................ 3 changes to table 7 and table 8................................................. 15 updated outline dimensions ................................................... 21 changes to ordering guide ...................................................... 21 1/03data sheet changed from rev. 0 to rev. a changes to table iv ................................................................... 12 updated outline dimensions ........................................ 16
ADN2819 rev. b | page 3 of 24 specifications table 1. t a = t min to t max , vcc = v min to v max , vee = 0 v, c f = 4.7 f, slicep = slicen = vcc, unless otherwise noted. parameter conditions min typ max unit quantizerdc characteristics input voltage range @ pin or nin, dc-coupled 0 1.2 v peak-to-peak differential input 2.4 v input common-mode level dc-coupled (see figure 28) 0.4 v differential input sensitivity pin-nin, ac-coupled 1 , ber = 1 10 C10 4 10 mv p-p input overdrive see figure 8 2 5 mv p-p input offset 500 v input rms noise ber = 1 10 C10 244 v rms quantizerac characteristics upper C3 db bandwidth 1.9 ghz small signal gain differential 54 db s11 @ 2.5 ghz C15 db input resistance differential 100 ? input capacitance 0.65 pf pulse width distortion 2 10 ps quantizer slice adjustment gain slicepCslicen = 0.5 v 0.11 0.20 0.30 v/v control voltage range slicepCslicen C0.8 +0.8 v @ slicep or slicen 1.3 vcc v slice threshold offset 1.0 mv level signal detect (sdout) level detect range (see figure 4) r thresh = 2 ? 9.4 13.3 18.0 mv r thresh = 20 k? 2.5 5.3 7.6 mv r thresh = 90 k? 0.7 3.0 5.2 mv response time dc-coupled 0.1 0.3 5 s hysteresis (electrical) oc-48, prbs 2 23 r thresh = 2 k? 5.6 6.6 7.8 db r thresh = 20 k? 3.9 6.2 8.5 db r thresh = 90 k? 3.2 6.7 9.9 db oc-12, prbs 2 23 r thresh = 2 k? 4.7 6.4 7.8 db r thresh = 20 k? 1.8 6.0 10.0 db r thresh = 90 k? 6.3 db r thresh = 90 k? @ 25c 4.8 6.9 8.9 db oc-3, prbs 2 23 r thresh = 2 k? 3.6 6.2 8.5 db r thresh = 20 k? 5.6 db r thresh = 90 k? 5.6 db r thresh = 90 k? @ 25c 3.4 6.6 9.9 db oc-48, prbs 2 7 r thresh = 2 k? 5.6 6.6 7.8 db r thresh = 20 k? 3.9 6.2 8.5 db r thresh = 90 k? 3.2 6.7 9.9 db oc-12, prbs 2 7 r thresh = 2 k? 5.7 6.6 7.8 db r thresh = 20 k? 3.9 6.2 8.5 db r thresh = 90 k? 3.2 6.7 9.9 db
ADN2819 rev. b | page 4 of 24 parameter conditions min typ max unit hysteresis (electrical) (continued) oc-3, prbs 2 7 r thresh = 2 k? 5.4 6.6 7.7 db r thresh = 20 k? 4.6 6.4 8.2 db r thresh = 90 k? 3.9 6.8 9.7 db loss of lock detector (lol) loss of lock response time from f vco error > 1000 ppm 60 mv power supply voltage 3.0 3.3 3.6 v power supply current 150 164 215 ma phase-locked loop characteristics pinCnin = 10 mv p-p jitter transfer bw oc-48 590 880 khz gbe 310 480 khz oc-12 140 200 khz oc-3 48 85 khz jitter peaking oc-48 0.025 db oc-12 0.004 db oc-3 0.002 db jitter generation oc-48, 12 khzC20 mhz 0.003 ui rms 0.05 0.09 ui p-p oc-12, 12 khzC5 mhz 0.002 ui rms 0.02 0.04 ui p-p oc-3, 12 khzC1.3 mhz 0.002 ui rms 0.02 0.04 ui p-p jitter tolerance oc-48 (see figure 14) 600 hz 3 92 ui p-p 6 khz 3 20 ui p-p 100 khz 5.5 ui p-p 1 mhz 3 1.0 ui p-p gbe (oc-24) (see figure 14) 300 hz 3 16 ui p-p 3 khz 3 16 ui p-p 50 khz 7.7 ui p-p 500 khz 3 2.2 ui p-p oc-12 (see figure 14) 30 hz 3 100 ui p-p 300 hz 44 ui p-p 25 khz 5.8 ui p-p 250 khz 3 1.0 ui p-p oc-3 (see figure 14) 30 hz 3 50 ui p-p 300 hz 3 23.5 ui p-p 6500 hz 6.0 ui p-p 65 khz 3 1.0 ui p-p cml outputs (clkoutp/n, dataoutp/n) single-ended output swing v se (see figure 7) 300 455 600 mv differential output swing v diff (see figure 7) 600 910 1200 mv output high voltage v oh vcc v output low voltage v ol , referred to vcc C0.60 C0.30 v rise time 20%C80% 150 ps fall time 80%C20% 150 ps
ADN2819 rev. b | page 5 of 24 parameter conditions min typ max unit setup time t s (see figure 3) oc-48 140 ps gbe 350 ps oc-12 750 ps oc-3 3145 ps hold time t h (see figure 3) oc-48 150 ps gbe 350 ps oc-12 750 ps oc-3 3150 ps refclk dc input characteristics input voltage range @ refclkp or refclkn 0 vcc v peak-to-peak differential input 100 mv common-mode level dc-coupled, single-ended vcc/2 v test data dc input characteristics 4 (tdinp/n) cml inputs peak-to-peak differential input voltage 0.8 v lvttl dc input characteristics input high voltage v ih 2.0 v input low voltage v il 0.8 v input current v in = 0.4 v or v in = 2.4 v C5 +5 a input current (sel0 and sel1 only) 5 v in = 0.4 v or v in = 2.4 v C5 +50 a lvttl dc output characteristics output high voltage v oh , i oh = C2.0 ma 2.4 v output low voltage v ol , i ol = +2.0 ma 0.4 v 1 pin and nin should be differentially driv en, ac-coupled for optimum sensitivity. 2 pwd measurement made on quantizer outputs in bypass mode. 3 jitter tolerance measurements are equipment limited. 4 tdinp/n are cml inputs. if the drivers to the tdinp/n inpu ts are anything other than cml, they must be ac-coupled. 5 sel0 and sel1 have internal pull-down resistors, causing higher i ih .
ADN2819 r e v. b | pa ge 6 o f 2 4 absolute maximum ratings table 2. p a r a m e t e r r a t i n g supply voltage (vcc) 5.5 v minimum input voltage (all inputs) vee C 0.4 v m a ximum input voltage ( a ll inputs) vcc + 0.4 v maximum junction temperature 165c storage temperature C65c to +150c lead temperature (soldering 10 sec) 300c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . thermal c h aracteristics therma l resista n ce 48-le ad lfcs p , 4-la yer bo a r d wi th exp o s e d p a ddle s o lder e d to v c c ja = 25c/w esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ADN2819 r e v. b | pa ge 7 o f 2 4 pin conf iguration and fu nction descriptions pin 1 indica t o r t o p view ADN2819 thradj 1 vcc 2 vee 3 vref 4 pin 5 nin 6 slicep 7 slicen 8 vee 9 lol 10 xo1 11 xo2 12 re fclkn 1 3 refclkp 14 r e fsel 15 vee 16 tdinp 17 tdinn 1 8 vee 19 v cc 2 0 c f 1 21 vee 22 r e fsel1 23 r e fsel0 24 36 vcc 35 vcc 34 vee 33 vee 32 sel0 31 sel1 30 sel2 29 vee 28 vcc 27 vee 26 vcc 25 cf2 48 loopen 47 vc c 46 vee 45 sd ou t 44 b y pa ss 43 vee 42 vee 4 1 clk o utp 4 0 clk o utn 39 sq u e lc h 3 8 dataoutp 3 7 dataoutn 02999-b - 002 f i g u re 2. 48-l e ad l f csp p i n conf ig ur a t ion ta ble 3. pi n f u nct i on d e s c ri pt i o ns pin numb er mnemonic type 1 descr iption 1 thradj ai los threshold s e tting resistor. 2, 26, 28, pad vcc p analog sup p ly. 3, 9, 16, 19, 22, 2 7 , 29, 33, 34, 4 2 , 43, 46 vee p ground. 4 vref ao internal vref voltage. de coup le t o gn d with 0. 1 f ca pa citor . 5 pin ai differential data input. 6 nin ai d i fferential d a ta input. 7 slicep ai differential slice level ad just inp u t. 8 slicen ai differential slice level ad just inp u t. 10 lol do loss of lock indi cator. lvttl a c ti ve high. 11 xo1 ao crystal oscillator. 12 xo2 ao crystal oscillator. 13 refclkn di differential refclk input. lv ttl, lvcm os, lvpecl , lvds (lvpecl, l v ds on ly at 1 55. 52 mh z). 14 refclkp di differential refclk input. lv ttl, lvcm os, lvpecl , lvds (lvpecl, l v ds on ly at 1 55. 52 mh z). 15 refsel d i referenc e source sel e c t . 0 = on-chip osc i l l a to r w i th external c r ystal; 1 = external cl oc k sourc e , lv t t l . 17 tdin p ai dif f e r e ntia l test da ta input. c m l. 18 tdin n ai dif f e r e ntia l test da ta input. c m l. 20, 47 vcc p digital supp ly. 21 cf1 ao frequency lo op capacitor. 23 refsel1 di reference frequency se le ct (see table 6) lvttl. 24 refsel0 di reference frequency se le ct (see table 6) lvttl. 25 cf2 ao frequency lo op capacitor. 30 sel2 di data rate se lect (see table 5) lvttl. 31 sel1 di data rate se lect (see table 5) lvttl. 32 sel0 di data rate se lect (see table 5) lvttl. 35, 36 vcc p output driver supply. 37 da tao u tn do dif f e r e ntia l r e tim e d da ta outpu t . c m l. 38 da tao u t p do dif f e r e ntia l r e tim e d da ta outpu t . c m l. 39 squelc h di disable c l ock an d data outputs. active high. lvttl. 40 clkout n d o d i fferential rec o vered cl oc k output. cml. 41 clkout p d o d i fferential rec o vered cl oc k output. cml. 44 bypass d i bypass cd r mode. ac tive high. lv t t l . 45 sdo u t do loss of sig n a l de tect out p ut. acti v e hig h . lvttl. 48 loo p en di ena b le test da ta inputs. activ e hig h . lvttl. 1 type: p = pow e r, ai = an a l og in put , a o = an a l og out p ut , d i = d i g i t a l in put , d o = d i g i t a l out p u t .
ADN2819 r e v. b | pa ge 8 o f 2 4 t s t h clk outp d a t a outp/n 02999-b - 003 fi g u r e 3 . o u t p u t t i m i n g resistance (k ? ) 0 100 18 16 0 mv 8 6 4 2 12 10 14 thradj resist or vs. los trip point 10 20 30 40 50 60 70 80 90 02999-b - 004 f i g u re 4. l o s co mp ar ato r t r ip p o int prog r a m m i n g 01 123 456 78 9 02999-b - 005 0 hysteresis (db) 10 9 0 fre q ue ncy 5 4 3 2 7 6 8 1 f i g u re 5. l o s h y s t e r es is o c - 3 , C4 0c, 3 . 6 v , 2 23 C 1 p r bs input p a tt ern, r th = 9 0 k? hysteresis (db) 18 16 0 fre q ue ncy 8 6 4 2 12 10 14 02999-b - 006 01 123 45 678 9 0 f i g u re 6. l o s h y s t e r es is o c - 12, C 4 0 c, 3.6 v , 2 23 C 1 p r bs input p a tt ern, r th = 90 k? out p out n v se v cml 0v outp?outn v se v diff 02999-b - 007 f i gure 7. s i ngl e -e n d ed v s . d i fferenti a l o u tput specif i c a tio n s
ADN2819 r e v. b | pa ge 9 o f 2 4 definition of terms maximum, minimum, and typical specificati o ns s p e c if ic a t io n s fo r e v er y p a ra m e t e r a r e der i v e d f r o m st a t ist i ca l a n a l y s es o f da t a t a k e n on m u l t i p le de vices f r o m m u l t i p le wa fe r lo ts. t y p i ca l sp e c if ica t ion s a r e t h e m e an o f t h e dist r i b u t i o n o f th e da ta f o r tha t p a ra m e ter . i f a p a ra m e ter has a maxim u m (o r a minim u m), tha t val u e is calc u l a t ed b y addin g t o (o r s u b t rac t in g f r o m ) th e m e a n si x ti m e s t h e s t a n d a r d devia t i o n o f th e di st r i but i on. th i s pro c e d u r e i s i n te nd e d to tol e r a te pro d u c t i on va r i a t ion s . i f t h e m e a n shif ts b y 1.5 st anda r d d e v i a t ion s , t h e r e ma inin g 4 . 5 st a nda rd d e v i a t ion s st i l l p r o v id e a fa i l ur e ra t e o f o n l y 3 . 4 pa r t s pe r m i ll i o n . f o r all t e s t ed pa r a m e t e r s , th e t e s t limi ts a r e gua r db a nde d to accoun t fo r tester var i a t ion an d t h er efo r e gua r an t e e t h a t n o de v i ce is s h i p p e d ou tside o f da t a sh e e t sp e c if ic a t i o n s . inpu t sensi t ivity an d inpu t o v erdrive s e n s i t i v i t y a nd o v er dr i v e s p e c if ica t ion s fo r t h e q u an t i zer i n v o lv e of f s e t vol t age, g a i n , and noi s e. the rel a t i onship b e t w e e n t h e logi c o u t p u t o f th e q u a n tiz e r a n d th e a n alog v o l t a g e in p u t i s show n i n f i g u re 8 . f o r a su f f i c i en t l y l a rge p o s i t i ve i n put vol t age , th e o u t p u t is alwa ys l o g i c 1; simila rl y f o r n e g a ti v e in p u ts, t h e o u t p u t i s al wa ys logi c 0. h o w e v e r , th e tra n si ti o n s bet w e e n o u t p ut l o g i c l e vels 1 a nd 0 a r e n o t a t p r e c is ely def i n e d i n p u t v o l t a g e le ve ls, b u t o c c u r o v er a ra n g e o f in p u t vol t a g es. w i t h i n t h i s z o ne of c o n f u s i o n , t h e output m a y b e e i t h e r 1 or 0 , or it m a y ev en f a il t o a t ta in a valid log i c s t a t e . the wid t h of this zo ne is det e r m i n e d b y t h e i n p u t v o l t a g e n o is e o f t h e qu a n t i zer . th e ce n t e r o f th e z o n e o f co n f usi o n i s th e q u a n tiz e r i n p u t o f fse t v o l t a g e . i n p u t ov er dr i v e is t h e ma g n i t ude o f si g n al r e q u ir e d t o gua r a n te e t h e c o r r e c t log i c le v e l wi t h 1 10 C10 co nf iden ce leve l. 0 1 input (v p-p) o u tput n oise sensitivity (2 overdrive) o ffset o verdrive 02999-b - 008 f i gure 8. input s e n s itivit y and input o v er driv e single-ended vs. differential a c -co u pling is typ i ca l l y us e d to dr i v e t h e i n p u ts t o t h e q u an t i zer . t h e i n p u ts a r e in t e r n a l ly dc b i as e d t o a co m m on- m o de p o ten t ial o f ~0.6 v . dr i v in g th e adn281 9 sin g le-en d e d a nd obs e r v in g t h e quan t i zer i n p u t wi t h a n os ci l l os co p e p r ob e a t t h e p o in t i n di ca te d i n f i gur e 9 sh o w s a b i na r y sig n a l w i t h an a v era g e v a l u e e q ual t o t h e co mm on- m o d e p o ten t ial an d in s t an t a ne o u s val u es a b o v e an d b e lo w t h e a v erag e val u e . i t is co n v e n ien t t o m e as ur e t h e p e ak-t o- p e a k a m pli t ude o f t h is sig n al a nd t o c a l l t h e mini m u m r e q u ir e d val u e t h e quan t i zer s e n s it i v it y . r e f e r r i n g t o fi g u re 8 , s i n c e b o t h p o s i t i v e a n d ne g a t i v e of f s e t s ne e d to b e a c c o m m o d a t e d, t h e s e ns i t i v i t y i s t w ice t h e o v er dr i v e . 50 ? 50 ? q u antizer + ADN2819 vref pin scope pr obe vref 10mv p-p 02999-b - 009 f i gure 9. s i ngle -en d ed s e nsitivit y me asur e m ent 50 ? 50 ? q u antizer + ADN2819 vref nin pin s cope pr obe vref 5mv p-p 02999-b - 010 f i g u re 10. d i f f e r e nt ia l s e ns it iv it y m e as ur e m ent dr i v in g t h e ADN2819 dif f er en t i al l y (s ee f i gur e 10), s e n s i t ivi t y s e em s t o im p r o v e b y obs e r v in g t h e quan t i zer i n p u t wi t h a n os cil l os co p e p r obe . this is a n il l u sio n ca us e d b y th e us e o f a sin g le-e n d e d p r obe . a 5 mv p - p sig n al a p p e a r s t o dr i v e th e ad n2819 q u a n tizer . h o w e v e r , t h e sin g le-en d ed p r obe m e as ur es o n l y h a lf th e si g n al . t h e tr ue q u a n tiz e r in p u t si gn al i s tw i c e th i s val u e since t h e o t h e r q u a n t i zer in p u t is co m p le m e n t a r y t o t h e sig n al bein g obs e r v e d .
ADN2819 rev. b | page 10 of 24 los response time the l o s r e s p on s e t i m e is t h e de l a y b e tw e e n t h e r e m o val o f t h e in p u t sig n al an d indic a tion o f los s o f sig n al (l os) a t s d o u t . the ADN2819 s r e s p o n s e time is 300 n s typ w h en t h e in p u ts a r e d c - c o u p l e d . i n p r a c ti ce , th e tim e co n s ta n t o f a c - c o u p l i n g a t t h e q u an t i zer i n p u t det e r m i n es t h e los r e sp o n s e t i m e . jitter specifications the ADN2819 cd r is desig n e d t o ac hiev e t h e bes t b i t-er r o r - ra t e (ber) p e r f o r ma n c e , and has exce e d e d t h e ji t t er t r a n sfer , gen e r a t i o n , and t o lera n c e sp e c if ica t ion s p r o p os e d fo r sonet/s d h e q ui pm e n t def i ne d i n t h e t e lco r di a t e ch n o lo g i es sp e c if ic a t ion. j i t t e r is the d y na mic dis p lacemen t o f d i gi t a l s i gn a l e d g e s fr o m t h eir lo n g - t er m a v era g e p o si t i on s m e as ur e d in ui (uni t in t e r v als), w h er e 1 ui = 1 b i t p e r i o d . j i t t e r o n t h e in p u t da t a ca n ca us e d y namic p h as e er r o rs o n the r e co v e r e d c l o c k s a m p ling e d g e . j i t t e r o n t h e r e co v e r e d clo c k c a u s es ji t t er on t h e r e ti m e d da ta . the fol l o w in g s e c t io n s summ a r iz e t h e sp e c if ic a t io n s o f t h e ji t t e r g e n e ra ti o n , tra n sf e r , a n d t o le ra n c e i n a c co r d a n ce wi th t h e t e lco r dia do c u m e n t (gr - 253-co re, i s s u e 3, s e p t em ber 2000 ) fo r t h e o p t i cal i n t e r f ace a t t h e e q ui pm e n t le ve l , a nd t h e ad n2819 p e r f o r ma n c e wi th r e sp ec t t o t h os e s p ecif ica t ion s . j i tte r ge ne ra tion j i t t e r ge n e ra t i on sp e c if ic a t ion li mi ts t h e am o u n t o f ji t t er t h a t ca n b e ge ner a te d b y t h e de vic e wi t h n o j i tter and wan d er a p plie d a t t h e in p u t. f o r o c -48 de vices, t h e b a nd-p a ss f i lter has a 12 k h z h i g h -p ass c u t o f f f r e q uen c y , w i t h a r o l l -o f f o f 20 db/d e c ad e and a lo w-p a ss c u t o f f f r e q uen c y o f a t le ast 20 mh z. the ji t t e r g e n e r a t e d sho u ld be les s than 0.01 ui r m s a nd 0.1 ui p - p . jitter transfer j i t t e r tra n sf e r fun c ti o n i s th e ra t i o o f th e j i t t e r o n th e o u t p u t sig n al t o t h e ji t t er a p plie d o n t h e in p u t sig n al v e rs us t h e f r eq uen c y . t h is p a ra m e ter m e asur es th e limi t e d a m o u n t o f ji t t e r o n a n in p u t sig n al tha t ca n b e t r a n sfer r e d t o the o u t p u t sig n al (s ee f i gur e 11). slope = ? 20db/decade jitter freq uency (khz) 0.1 j i tte r gain (db) f c a ccept abl e range 02999-b - 011 f i gure 11. j i tter t r a n sfer cur v e j i tte r tole ra nc e j i t t e r t o leran c e is def i ne d as t h e p e ak- t o-p e ak am pli t ude o f t h e sin u s o id a l j i t t e r a p plie d o n t h e i n p u t sig n a l t h a t ca us es a 1 db p o w e r p e na l t y . this is a st r e ss test t h a t is in te nde d to e n sur e no addi t i o n a l p e na l t y is i n c u r r e d un der t h e op er a t i n g co ndi t i o n s (s ee f i gur e 12). f i gur e 13 s h o w s th e typ i cal o c -48 ji t t er t o lera n c e p e r f o r ma nce o f th e ad n2819. slope = ? 20db/decade f 0 f 1 f 2 f 3 f 4 jitter freq uency (hz) 15 1.5 0.15 i n p u t j i tte r amp l i t ude (ui ) 02999-b - 012 f i gure 12. sone t ji tter t o l e r a nce mas k modula t ion freq u ency (hz) 10 1k 100k 10m 100 10 0.1 a m p l itude (ui p - p ) 1 100 10k 1m 1 ADN2819 oc-48 sonet ma s k 02999-b - 013 f i g u re 13. o c -4 8 j i t t er t o ler a nce cur v e
ADN2819 rev. b | page 11 of 24 0.5 0 ? 0.5 ? 1.0 ? 1.5 ? 2.0 ? 2.5 ? 3.0 ? 3.5 ? 4.0 ? 4.5 ? 5.0 ? 5.5 ? 6.0 ? 6.5 ? 7.0 ? 7.5 ? 8.0 ? 9.0 ? 9.5 ?10.0 ? 8.5 1k 10k 100k 1m 100m frequency (hz) 10m oc3_jit_tolerance gbe_jit_tolerance oc3_jit_transfer gbe_jit_transfer oc12_jit_tolerance oc48_jit_tolerance oc12_jit_transfer oc48_jit_transfer 02999-b - 014 f i gur e 1 4 . ji tt e r t r ansfe r and ji tt er t r ac k i ng bw table 4. jitter transfer a n d tole rance: so n e t spec vs. ADN2819 jitter transfer jitter tolerance rate sonet spec (f c ) ADN2819 (khz) implementation margin mask corner frequency ADN2819 sonet spec (ui p-p) ADN2819 (ui p-p) implementation margin 1 oc-48 2 mhz 590 3.4 1 mhz 4.8 mhz 0.15 1.0 6.67 oc-12 500 khz 140 3.6 250 khz 4.8 mhz 0.15 1.0 6.67 oc-3 130 khz 48 2.7 65 khz 600 khz 0.15 1.0 6.67 1 jitter tol e rance meas urements l imited by tes t equipment capabil i ties .
ADN2819 rev. b | page 12 of 24 theory of operation the ADN2819 is a dela y-lo ck e d a nd p h as e-lo ck ed lo o p cir c ui t fo r clo c k r e co ver y a n d da t a r e t i min g f r o m an nrz e n co de d da ta s t r e a m . th e p h a s e o f th e in p u t da t a si gn al i s tra c k e d b y t w o s e p a ra t e fe e d b a c k lo o p s tha t sha r e a co mm on c o n t r o l v o l t a g e . a hig h sp ee d del a y-lo c k e d lo o p p a th us es a v o l t ag e co n t r o l l ed phas e sh if t e r t o t r ack t h e hig h f r e q uen c y com p on e n ts o f t h e i n put j i tte r . a s e p a r a te ph a s e c o n t rol l o op , c o m p r i s e d of t h e v c o , tra c k s t h e l o w f r eq ue n c y co m p o n en t s o f th e in p u t ji t t e r . the in i t ia l f r e q uen c y o f t h e v c o is s e t b y a t h i r d lo o p t h a t co m p a r es t h e v c o f r e q uen c y wi t h t h e r e fer e nce f r e q uen c y and s e ts t h e co a r s e t u nin g v o l t a g e . th e ji t t er t r ack i ng phas e-lo ck e d lo o p co n t r o ls the v c o b y th e f i n e t u nin g co n t r o l . the dela y- an d phas e-lo ck e d lo o p s t o g e t h er t r ack t h e phas e o f t h e i n p u t da t a si g n al . f o r exa m ple , w h e n t h e clo c k la gs in p u t da t a , t h e phas e det e c t o r dr i v es t h e v c o t o a hig h er f r e q uen c y a nd i n cr e a s e s t h e de l a y t h r o ug h t h e phas e s h if t e r . b o t h o f t h es e ac t i o n s s e r v e t o r e d u ce t h e phas e er r o r b e tw e e n t h e clo c k an d da t a . the fast er clo c k p i cks u p phas e w h i l e t h e de l a ye d da t a los e s phas e . si nce t h e lo o p f i lt e r is a n in t e g r a t or , t h e st a t ic phas e e r ror i s d r ive n to z e ro . an o t h e r vi e w of t h e cir c ui t is t h a t t h e phas e s h if t e r im ple m e n t s th e z e r o r e q u i r e d f o r th e f r eq uen c y co m p e n s a tio n o f a seco n d - o r der p h as e-lo ck e d lo o p . this zer o is p l ace d in th e f e e d back p a t h and t h er efo r e do es n o t a p p e a r in t h e clos e d -lo o p t r a n sfer fun c ti o n . j i t t er peaki n g i n a co n v en ti o n al s e co n d - o r d e r p h a s e- lo c k e d lo o p is c a us ed b y t h e p r es en c e o f this zer o in th e c l os e d - loo p tra n sf e r fu n c ti o n . s i n c e th is ci r c ui t h a s n o z e r o i n t h e clos e d -lo o p t r an sfer , ji t t er p e a k in g is mi nim i z e d . the dela y- an d p h as e-lo ck e d lo o p s t o g e th er sim u l t an e o us l y p r o v ide wideb a nd j i tter acco m m o d a t ion an d n a r r o w -b a n d ji tter f i l t er in g. t h e li ne a r ize d b l o c k d i a g ra m i n f i gur e 15 sh o w s t h a t th e j i t t e r tra n sf er fun c ti o n , z ( s)/x (s), i s a seco n d - o r d e r lo w - pa s s p r o v idin g exce l l e n t f i l t er ing. n o t e t h a t t h e j i t t e r t r a n sfer has n o zer o , un li k e an o r dina r y s e co nd-o r der phas e-l o ck e d lo o p . thi s m e an s t h e ma in p ll lo o p has lo w ji t t er p e akin g (s ee f i gur e 16), w h ich ma k e s t h is cir c ui t ide a l fo r sig n a l r e gen e ra t o r a p pli c a - t i o n s w h er e ji t t e r p e akin g i n a c a s c ade o f r e g e nera t o rs can c o n t r i b u te to h a z a rdou s jit t e r a c c u m u l a t i on. d/sc o/s psh 1/n e(s) x(s) input da t a z(s ) reco vered clock d = phase detec t or gain o = vco gain c = loop integr a to r psh = phase shifter gain n = divide r a tio jitter transfer function z(s) x(s) 1 s 2 + s +1 cn do n psh o = tra cking err or transfer function e(s) x(s) s 2 s 2 + s + do cn d ps h c = 02999-b - 015 f i gure 15. pll/dll a r chit ectu r e the er r o r t r a n sf er , e(s)/x(s), has t h e s a me hig h - p as s fo r m as a n ord i n a r y ph a s e - l o cke d l o op . t h i s t r ans f e r f u nc t i on i s f r e e to b e o p t i mi ze d t o g i v e exce l l en t wideb a nd ji t t er acc o mmo da t i on sin c e t h e ji t t e r t r a n sfer f u n c t i o n , z(s)/x(s), p r o v ides t h e na r r o w - b a nd ji t t er f i l t er in g. s e e t a b l e 4 fo r err o r t r a n sfe r b a ndwid t h s a nd j i t t er t r a n sfer b a ndwid t h s a t t h e v a r i o u s da t a r a tes. the dela y-lo ck e d an d p h as e - lo c k e d lo o p s co n t r i b u t e t o o v eral l ji t t er accom m o d a t io n. a t lo w f r e q uen c ie s o f in p u t j i t t e r o n t h e da t a sig n a l , t h e in t e g r a t o r i n t h e lo o p f i l t er p r o v ides hig h gain t o t r ack la rg e ji t t er a m pli t udes wi t h smal l phas e er r o r . i n t h is cas e , t h e v c o is f r e q uen c y m o d u l a te d , a nd ji t t er is t r ack e d as in an ord i n a r y ph a s e - l o cke d l o op . t h e am ou n t of l o w f r e q u e nc y j i tt e r th a t ca n be tra c k e d i s a fun c ti o n o f th e v c o t u n i n g ra n g e . a wider t u ni n g r a n g e g i ves la rger acco m m o d a t ion o f lo w f r e q uen c y ji t t er . the i n t e r n al lo op co n t r o l v o l t a g e r e ma in s smal l fo r smal l phas e er r o rs, s o t h e phas e s h if t e r r e main s clos e t o t h e cen t er o f i t s rang e , a nd t h er efo r e co n t r i b u t e s l i t t le t o t h e lo w fr e q u e n c y j i t t e r a c c o m m od a t i o n . a t m e di u m j i t t e r f r e q uen c ies, t h e ga in and t u ni n g r a n g e o f t h e v c o a r e n o t la rg e en o u g h t o t r ack t h e i n p u t ji t t e r . i n t h is cas e , t h e v c o con t r o l v o l t a g e b e comes la rg e an d s a t u ra t e s, an d t h e v c o f r e q ue n c y d w e l ls a t o n e o r t h e o t h e r ext r em e o f i t s t u nin g ra n g e . th e size o f t h e v c o t u ni n g ra n g e t h er efo r e has o n l y a smal l ef fe c t o n t h e ji t t er accomm o d a t ion. th e de l a y-lo ck e d lo o p co n t r o l v o l t a g e i s n o w la rg er ; t h us, t h e phas e s h i f t e r t a k e s o n t h e b u r d en o f t r ackin g t h e in p u t ji t t er . th e phas e s h if t e r ra n g e , i n ui, ca n b e s e e n as a b r o a d pla t e a u o n t h e ji t t er tolera n c e c u r v e . the phas e s h if ter has a minim u m ra n g e o f 2 ui a t al l da t a ra tes.
ADN2819 rev. b | page 13 of 24 t h e g a i n of t h e l o op i n te g r a t or i s s m a l l f o r h i g h j i tte r f r e q uen c ies, s o l a rg er phas e dif f er en ces a r e n e e d e d t o ma k e t h e lo o p co n t r o l v o l t a g e b i g e n o u g h t o t u n e t h e ra ng e o f t h e phas e sh i f te r . l a rge ph a s e e r rors a t h i g h j i tte r f r e q u e nc i e s c a n n ot b e t o le ra t e d . i n th is r e gi o n , th e ga in o f th e in t e gra t o r d e t e rm in e s t h e ji t t er accomm o d a t ion. si n c e t h e ga i n o f t h e lo o p in teg r a t o r dec l in es lin e a r l y wi t h f r eq uen c y , ji t t er accomm o d a t io n is lo w e r wi t h hig h er ji t t e r f r e q uen c y . a t t h e hig h es t f r e q u e n c ies, t h e lo o p ga in is ver y sma l l a nd li t t le t u ni n g o f t h e pha s e shif ter c a n b e e x p e c t e d . i n t h i s c a s e , j i t t e r a c c o m m o d a t i o n i s d e t e r m i n e d b y t h e e y e o p eni n g o f t h e in p u t da t a , t h e s t a t ic phas e er r o r , a n d t h e re s i d u a l l o op j i tte r ge ne r a t i on. th e j i tte r a c c o mmo d a t i on i s r o ug hl y 0.5 ui in this r e g i o n . th e co r n er f r eq uen c y b e tween t h e de clini n g slo p e a nd t h e f l a t r e g i o n is t h e clo s e d -lo o p b a n d wi d t h o f th e dela y-lo ck e d lo o p , which is r o ug hl y 5 m h z f o r o c -12, o c -48, an d gbe da ta r a t e s, and 600 kh z f o r o c -3 da ta r a t e s . jitter peaking in ordinar y pll ADN2819 z(s) x(s) f (khz) jitter gain (d b ) o n ps h d psh c 02999-b - 016 f i g u re 16. j i t t er r e s p ons e v s . co nvent i ona l pll
ADN2819 rev. b | page 14 of 24 functional description multirate clock a n d dat a reco very the ADN2819 wil l r e co v e r c l o c k an d da t a f r o m s e r i al b i t s t r e a m s a t oc - 3 , oc - 1 2 , oc - 4 8 , a n d g b e d a t a r a t e s a s w e l l a s th e 15/14 fec r a t e s. th e ou t p u t o f th e 2.5 gh z v c o is divided do wn i n o r der to su p p o r t t h e lo w e r d a t a r a tes. the da t a r a te is s e le c t e d b y t h e s e l[2..0] in p u ts (s e e t a b l e 5). tab l e 5. data rate selection s e l [ 2 . . 0 ] r a t e f r e q u e n c y ( m h z ) 0 0 0 o c - 4 8 2 4 8 8 . 3 2 0 0 1 g b e 1 2 5 0 . 0 0 0 1 0 o c - 1 2 6 2 2 . 0 8 0 1 1 o c - 3 1 5 5 . 5 2 1 0 0 o c - 4 8 f e c 2 6 6 6 . 0 6 1 0 1 g b e f e c 1 3 3 9 . 2 9 1 1 0 o c - 1 2 f e c 6 6 6 . 5 1 1 1 1 o c - 3 f e c 1 6 6 . 6 3 limiting a m plifier the limi t i n g a m plif ier has dif f er en t i al i n p u ts (p i n / n in) t h a t are i n te r n a l ly te r m i n a t e d w i t h 5 0 ? to an on - c h i p volt age r e fer e n c e (vre f = 0.6 v typ i ca l l y). th es e i n p u t s a r e n o r m al l y a c - c oupl e d , a l t h ou g h d c - c oupl i n g i s p o ss i b l e a s l o ng a s t h e i n put co mm o n -mo d e v o l t a g e r e ma ins a b o v e 0.4 v (s ee f i gur e 26, f i gur e 27, a nd f i gur e 28 in t h e a p plica t ion s i n fo r m a t io n s e c t io n). i n p u t o f fs et is fac t o r y t r imm e d t o achi e v e b e t t er t h an 4 mv typ i cal s e n s i t ivi t y wi t h minimal dr if t. the limi t i n g a m plif ier can b e dr i v en dif f er en t i a l ly o r sin g le-e n d e d . slice adju st the q u a n t i zer s l icin g leve l can b e o f fs et b y 100 mv t o mi tig a t e t h e ef fe c t o f a m plif ie d sp on t a ne o u s emissio n (as e ) n o is e b y a p pl yi n g a dif f er en t i al v o l t a g e i n p u t o f 0.8 v to s l i c ep/ n in p u ts. i f n o a d j u st m e n t o f t h e slice le v e l is ne e d e d , s l icep/ n shou l d b e t i e d to v c c . loss of sig n al (los ) detector the r e cei v er f r o n t e nd le vel sig n a l dete c t c i r c ui t indic a te s w h e n t h e i n p u t sig n al le v e l has f a l l en b e lo w a us er ad j u s t a b le t h re sho l d. t h e t h re sho l d i s s e t w i t h a s i ng l e e x t e r n a l re s i stor f r o m p i n 1, th rad j , t o g n d . the l o s com p ara t o r tr i p p o in t v e rsus t h e r e sisto r va l u e is i l l u st ra t e d in f i gur e 4 (t his is o n ly v a l i d f o r sl ic e p = sl ic e n = v c c ) . i f t h e i n p u t l e vel to t h e ad n2819 dr o p s be lo w t h e p r og ra mm e d los thr e s h old , s d o u t (p in 45) wil l in dic a t e t h e los s o f sig n al co n d i t ion wi t h a l o g i c 1. th e l o s r e s p o n s e time is ~300 n s b y desig n , b u t i t is do min a te d b y t h e rc t i m e const a n t in ac-co u ple d a p pli c a t io n s . i f th e l o s d e t e c t o r i s used , th e q u a n tiz e r s l i c e ad j u s t p i n s m u s t b o t h b e t i e d t o v c c. this is t o a v o i d in t e rac t ion w i t h t h e los t h re shol d l e vel. n o t e t h a t i t is no t exp e c t e d t o us e b o t h l o s and s l ice ad j u s t a t t h e s a me t i m e . s y s t em s wi t h o p t i cal am plif iers ne e d t h e s l ice ad j u st t o e v ad e a s e. h o w e ver , a loss o f sig n a l in a n op t i ca l li n k th a t use s o p tical a m p l i f i e r s ca use s th e o p tical a m p l i f i e r o u t p u t to b e f u l l -s ca le n o is e. u n der t h i s co ndi t i on, t h e los w o u l d n o t det e c t t h e fail ur e . i n this c a s e , t h e los s o f lo c k s i g n al in dica t e s t h e fai l ur e b e c a us e t h e cdr circ ui t r y is una b le t o lo ck o n t o a sig n a l t h a t is f u l l -s ca le n o is e . reference clock ther e a r e t h r e e o p t i o n s fo r p r o v idin g t h e r e fer e n c e f r e q ue n c y to th e ad n2819: dif f er en tial c l o c k, sin g le-en d ed c l o c k, o r cr ys tal os cil l a t o r . s e e f i gur e 17, f i gur e 18, a n d f i gur e 19 f o r exa m p l e co nf igura t io n s . 100k ? 100k ? b u ffer ADN2819 vcc/2 refclkn refclkp cr yst al oscilla t o r xo1 xo2 vcc vcc vcc refsel 02999-b - 017 f i g u re 17. d i f f e r e nt ia l r e fclk conf ig u r at i o n out 100k ? 100k ? b u ffer ADN2819 vcc/2 refclkn refclk p cr yst al oscilla t o r xo 1 xo 2 vcc vcc vcc refsel cl k os c vcc nc 02999-b - 018 f i gure 18. sing le -ended ref c lk c o nf igur ation
ADN2819 rev. b | page 15 of 24 100k ? 100k ? b u ffer ADN2819 vcc/2 refclkn refclk p cr yst al oscilla t o r xo 1 xo 2 refsel nc 19.44mhz vcc 02999-b - 019 f i g u re 19. cr y s t a l o s cil l a t or co nf ig ur at ion the ADN2819 ca n accep t an y o f th e f o l l o w in g r e f e r e n c e c l o c k f r eq uen c ies: 19. 44 mh z, 38.88 mh z, and 77.76 mh z a t l v t t l / l v cm os/l vpecl/l v ds l e v e ls, o r 155.52 m h z a t l v p e cl/ l v d s l e v e l s vi a th e r e fcl k n / p i n p u t s , in d e p e n d en t o f d a ta ra t e (in c l u din g g i ga b i t e t h e r n et a n d wra p p e r ra t e s). th e in p u t b u f f er a ccep t s a n y d i f f er en t i al si gn al wi th a pea k - t o-peak dif f er en tial a m pli t ude o f g r ea t e r tha n 100 mv (e.g., l v p e cl o r l v ds) o r a st anda r d si n g le-e nd e d lo w vol t a g e t t l i n p u t, p r o v idin g maxi m u m syst em f l e x i b i l i t y . the a ppr o p r i a t e division ra tio can b e s e le c t ed usin g t h e refs el0/1 p i n s , acco r d in g t o t a b l e 6. p h as e no is e an d d u ty c y cle o f t h e r e fer e n c e clo c k a r e n o t cr i t ical , an d 100 p p m acc u rac y is s u f f i cien t. ta ble 6. r e fere nce f r equenc y select i o n r e f s e l r e f s e l [ 1 . . 0 ] applied refer e nce frequency (mhz) 1 00 19.44 1 01 38.88 1 10 77.76 1 11 155.52 0 xx refclkp/n inactive. use 19.44 mhz xtal on pins x o 1, xo2 (pull refclkp to vcc) an o n -chi p os ci l l a t o r t o be us e d wi t h an ext e r n al cr ys tal is als o prov i d e d a s an a l te r n a t iv e to u s i n g t h e r e f c l k n / p i n put s . de ta ils o f th e r e co mm en d e d cr ys tal a r e gi v e n in t a b l e 7. table 7. required cry s tal sp ec ification s parameter value mode series res o nant frequency/ov e r a ll stabi l ity 19.44 mhz 10 0 ppm frequency accuracy 100 ppm temperature stability 100 ppm aging 100 ppm esr 50 ? max r e fs el m u s t b e ti ed t o v c c w h en th e r e fc lk n/ p in p u t s a r e a c ti v e , o r ti ed t o v ee wh e n t h e oscilla t o r i s use d . n o co nn ecti o n b e tw e e n t h e x o p i n and t h e re f c lk i n p u t is ne cess a r y (s e e f i gur e 17, f i gur e 18, a nd f i gur e 19). n o t e tha t th e cr ys tal sh o u ld o p era t e in s e r i es r e s o na n t m o de , w h ich r e n d ers i t ins e n s i t i v e to e x t e rn al pa ra si ti cs. n o tri m m i n g ca pa ci t o r s a r e r e q u i r ed . lock de tec t or o p eratio n the lo ck de t e c t o r m o ni t o rs t h e f r e q uen c y dif f er en c e b e tw e e n t h e v c o an d t h e r e fer e n c e clo c k, a nd de as s e r t s t h e los s o f lo ck sig n al w h en t h e v c o is wi thin 500 p p m o f cen t er f r eq uen c y . t h i s e n a b le s th e p h a s e loo p , wh ic h th en m a i n ta in s p h a s e lock , unles s t h e f r e q u e n c y er r o r excee d s 0.1%. sh o u ld t h is o c c u r , t h e los s o f lo c k sig n al is r e as s e r t e d a nd co n t r o l r e t u r n s t o th e f r e- q u en c y lo o p , w h ich wi l l r e acq u ir e a nd main t a i n a st a b le clo c k sig n al a t t h e o u t p u t . th e f r e q ue n c y lo o p r e q u ir es a sin g le ext e r - nal ca p a c i t o r betw een cf1 an d cf2. th e ca p a c i t o r s p ecif ic a t ion is g i v e n i n t a b l e 8. table 8. r e com m ende d c f ca p a citor sp ecification parameter value temperature range C40c to +85c capacitance >3.0 f leakage <80 na rating >6.3 v 1000 500 0 500 1000 f vco err o r ( ppm) lol 1 02999-b - 020 f i g u re 20. t r ans f er f u nc t i on l o l
ADN2819 rev. b | page 16 of 24 50 ? 50 ? q u antizer + ADN2819 vref nin pi n 50 ? 50 ? vc c tdinp/n loopen byp a ss cdr retimed d a t a clk 0 1 10 d a t a outp/n c lk outp/ n s q u elch fr om q u antizer output 02999-b - 021 f i gur e 2 1 . t e st m o d e s squelch m o de w h en t h e s q ue l c h in p u t is dr i v en t o a t t l hig h s t a t e , the c l o c k a nd da t a o u t p ut s a r e s e t to t h e z e r o st a t e to su pp r e ss do wn - st r e a m p r o c ess i n g . i f desir e d , t h is p i n c a n b e dire c t ly dr i v en b y t h e l o s ( l o s s of s i g n a l ) d e te c t or output ( s d o u t ) . i f t h e sq ue lc h fun c ti o n i s n o t r e q u i r e d , th e p i n sh o u ld b e ti e d t o v e e. test mode s: bypass and loopback w h en t h e b y p a ss in p u t is dr i v en t o a t t l hig h sta t e , th e q u a n tiz e r o u t p u t i s co nn ect e d di r e ctl y t o th e b u f f e r s d r i v i n g th e da ta o u t p i n s , th us b y pa s s i n g th e c l oc k r e co v e r y ci r c ui t (see f i gur e 21). this fe a t ur e can h e l p t h e sys t em de al w i t h n o nst a nda r d b i t r a tes. the lo o p b a ck m o d e can b e i n vok e d b y dr i v i n g t h e lo open p i n to a t t l hi g h st a t e, w h ic h f a c i l i t a te s s y ste m di ag no st ic te st i n g . th i s c o nne c t s t h e te s t i n put s ( t di np / n ) to t h e cl o c k an d d a t a re c o ve r y c i rc u i t ( p e r f i g u re 2 1 ) . t h e t e st i n put s h a ve in t e r n a l 50 ? t e r m ina t io n s , and ca n b e lef t f l o a t i n g w h e n n o t i n us e. tdinp / n ar e cml in pu ts a nd can o n ly b e dc-co u ple d w h en b e i n g dr iv en b y cml o u t p u t s. th e td i n p/ n i n p u ts m u s t b e a c - c oupl e d i f d r ive n by a n y t h i ng ot he r t h an c m l output s . by p a ss and l o opb a ck mo de s are m u t u a l ly e x cl u s ive : on ly one of th es e m o des can b e us ed a t an y g i v e n time . th e ad n2819 is p u t in t o an i n de t e r m ina t e st a t e if b o t h t h e byp a ss a nd lo ope n p i n s a r e s e t t o l o g i c 1 a t t h e s a m e t i m e .
ADN2819 rev. b | page 17 of 24 applications information pcb design guidelines proper rf pcb design techniques must be used for optimal performance. power supply connections and ground planes use of one low impedance ground plane to both analog and digital grounds is recommended. the vee pins should be soldered directly to the ground plane to reduce series inductance. if the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias may be used in parallel to reduce the series inductance, especially on pins 33 and 34, which are the ground returns for the output buffers. use of a 10 f electrolytic capacitor between vcc and gnd is recommended at the location where the 3.3 v supply enters the pcb. use of 0.1 f and 1 nf ceramic chip capacitors should be placed between ic power supply vcc and gnd as close as possible to the ADN2819 vcc pins. again, if connections to the supply and ground are made through vias, the use of multiple vias in parallel will help to reduce series inductance, especially on pins 35 and 36, which supply power to the high speed clkoutp/n and dataoutp/n output buffers. refer to the schematic in figure 22 for recommended connections. transmission lines use of 50 ? transmission lines are required for all high frequency input and output signals to minimize reflections, including pin, nin, clkoutp, clkoutn, dataoutp, and dataoutn (also refclkp/n for a 155.52 mhz refclk). it is also recommended that the pin/nin input traces are matched in length and that the clkoutp/n and dataoutp/n traces are matched in length. all high speed cml outputs, clkoutp/n and dataoutp/n, also require 100 ? back termination chip re sistors connected between the output pin and vcc. these resistors should be placed as close as possible to the output pins. these 100 ? resistors are in parallel with on-chip 100 ? termination resistors to create a 50 ? back termination (see figure 23). the high speed inputs, pin and nin, are internally terminated with 50 ? to an internal reference voltage (see figure 24). a 0.1 f capacitor is recommended between vref, pin 4, and gnd to provide an ac ground for the inputs. as with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. soldering guidelines for chip scale package the lands on the 48-lead lfcsp are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central exposed pad. the pad on the printed circuit board should be at least as large as this exposed pad. the user must connect the exposed pad to analog vcc. if vias are used, they should be incorporated into the pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm; the via barrel should be plated with 1 oz. copper to plug the via.
ADN2819 rev. b | page 18 of 24 ADN2819 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 1nf 0.1 f 1nf 0.1 f thradj vcc vee vref pin nin slice p slicen vee lol xo1 xo2 vcc c in 50 ? r th 1nf 0.1 f 0.1 f 50 ? tia vcc 19.44mhz c refclkn refclkp r e fsel vee tdinp tdinn vee vc c cf1 vee r e fsel1 r e fsel0 nc vc c nc nc c c 4.7 f (see t able 8 for specs) 1n f 0.1 f vcc vcc vcc vee vee sel0 sel1 sel2 vee vcc vee vcc cf2 c vcc loopen vc c vee sd ou t b ypa ss vee vee clk o utp clk o utn sq u e lc h dataoutp dataoutn c 1n f 0.1 f 10 f vcc 50 ? transmission lines clk outp clk outn d a t a out p d a t a out n vcc 4 100 ? exposed p a d tied off t o vcc plane with vias 1nf 0.1 f vcc 02999-b - 022 f i gure 22. t y pic a l a p plic at ion cir c u i t 100 ? 50 ? ADN2819 50 ? 50 ? 100 ? vcc 100 ? 100 ? vc c 0.1 f 0.1 f 50 ? v term v term 02999-b - 023 f i g u re 23. a c - c oup l ed o u t p ut conf ig u r at i o n 50 ? 50 ? ADN2819 0.1 f nin pin c in c in 50 ? tia vref vcc 50 ? 02999-b - 024 f i g u r e 2 4 . a c - c o u pl e d i n pu t c o n f i g u r a t i o n
ADN2819 rev. b | page 19 of 24 choos ing ac-coupling capacitors t h e c h oi c e of a c - c oupl i n g c a p a c i tor s a t t h e i n put ( p i n , n i n ) a nd o u t p u t ( d a t a o utp , d a t a o u tn) o f th e ad n2819 m u st b e ch os e n s u ch t h a t t h e de vice w o rks p r o p erl y a t t h e lo w e r o c -3 and hig h er o c -48 da t a ra t e s. w h en ch o o s in g the ca pa ci t o r s , th e t i m e co n s ta n t f o rm ed wi th t h e tw o 50 ? r e si s t o r s in t h e sig n al p a t h m u s t b e con s i d er e d . w h e n a l a rg e n u m b er o f co n s e c u t i v e ide n t i cal dig i ts (ci d s) a r e a p pli e d , t h e ca p a c i t o r vol t a g e c a n dr o p d u e to b a s e li ne wan d er (s e e f i gur e 23), ca usin g p a t t er n dep e nd en t j i t t er (pd j ). f o r th e adn28 19 t o w o rk r o b u s t l y a t bo th o c -3 a nd o c -48, a minim u m ca p a ci t o r o f 1.6 f t o p i n/nin and 0.1 f o n d a t a ou tp/ d a t a o u t n sh ou ld b e us e d . thi s is b a s e d o n t h e as s u m p tion tha t 1000 cid s m u st be t o lera t e d and tha t t h e p d j s h o u ld b e limi t e d t o 0.01 ui p-p . 50 ? ADN2819 nin pin 50 ? v ref c in c in v2 v1 v2b v1 b tia limamp cdr c out c out d a t a outp d a t a outn + 4 3 2 1 v1 v1b v2 v2b v diff v diff = v2?v2b vth = ADN2819 q u antizer threshold v re f vth no tes 1. during d a t a p a tterns with high transition density , differential dc v o l t a ge a t v1 and v2 is 0. 2. when the output of the tia goes t o cid , v1 and v1b are driven t o different dc levels. v2 and v2b discharge t o the v ref level, which effectively introduces a differential dc offset a c r o ss the a c coupling capacitors. 3. when the b urst of d a t a st ar ts a gain, the differential dc offset a c r o ss the a c coupling cap a cit ors is applied t o the input levels, ca using a dc shift in the differential input . t his shift is large enough such tha t one of the st a tes, either high or lo w depending on the levels of v1 and v1b when the tia went t o cid , is cancelled out . the q u antizer will no t recognize this as a v a lid st a te. 4. the dc offset slo wl y discharges until the differential input v o l t a ge exceeds the sensitivity of the ADN2819. the q u antizer will be able t o recognize bo th high and lo w st a tes a t t his point . 02999-b - 025 f i gure 25. ex ample of base line w a nde r
ADN2819 rev. b | page 20 of 24 dc-cou pled ap plica t ion the in p u ts t o the ADN2819 can als o be dc-cou p l ed . this ma y b e n e ce s s a r y in b u rs t m o de a p plica t ion s w h er e t h er e a r e lo n g p e r i o d s of c i ds an d b a s e l i ne w a nd e r c a n n o t b e to l e r a te d. i f t h e in p u ts t o the ad n2819 a r e dc-co u p l ed , ca r e m u s t be t a k e n n o t t o viol a t e t h e in p u t ra n g e and c o mm on- m o d e l e v e l r e q u ir em en ts o f th e ad n2819 ( s ee f i gur e 26, f i gur e 27, a n d f i gur e 28). i f dc-co u plin g is r e quir e d , an d t h e ou t p ut le v e l s o f t h e ti a do n o t ad her e to t h e le vels sh own i n f i gur e 27 a n d f i gur e 28, t h er e n e e d s t o b e le vel s h if t i ng an d/o r a n a t ten u a t o r betw een t h e ti a o u t p u t s and t h e ad n2819 in p u ts. lol toggling during loss of input data i f th e in p u t da t a s t r e a m is los t d u e t o a b r ea k in th e o p tical link (o r f o r a n y r e as o n ), th e c l o c k ou t p u t f r o m the ad n2819 wil l s t a y wi thin 100 0 p p m o f the v c o cen t er f r eq uen c y as lo n g as t h er e is a v a lid refer e n c e clo c k. the l o l p i n t o g g l es a t a r a t e o f s e ver a l k h z b e c a us e t h e lol p i n to g g l es b e tw e e n a l o g i c 1 a nd a l o g i c 0, while th e f r e q ue n c y lo o p a nd p h as e lo o p swa p con t rol o f t h e v c o . the cha i n o f e v en t s is as fol l o w s: ? the ADN2819 is lo c k e d t o t h e in p u t da t a s t r e am; l o l = 0. ? the i n p u t da t a st r e a m is los t d u e t o a b r e a k i n t h e li nk. the v c o f r eq uen c y dr if ts un til t h e f r eq uen c y er r o r is g r ea t e r tha n 1000 p p m. l o l is as s e r t e d t o a l o g i c 1 as c o n t r o l o f t h e v c o is p a s s e d b a ck t o t h e f r e q uen c y lo o p . ? t h e f r e q u e nc y l o op pu l l s t h e v c o to w i t h i n 5 0 0 ppm of it s cen t er f r eq uen c y . c o n t r o l o f th e v c o is p a s s e d bac k t o t h e phas e lo o p an d lol is de ass e r t e d t o a l o g i c 0. ? the phas e lo o p t r ies t o acq u ir e , b u t t h er e is n o i n p u t da t a p r es en t s o t h e v c o f r e q uen c y dr if ts. ? the v c o f r eq uen c y dr if ts un t i l th e f r eq uen c y er r o r is g r ea t e r tha n 10 00 p p m . l o l is as s e r t ed t o a l o g i c 1 as co n t r o l o f th e v c o is p a s s e d bac k t o the f r eq uen c y lo o p . this p r o c ess is rep e a t e d u n t i l a va lid i n p u t d a t a st r e a m is re -e st abl i she d . 50 ? 50 ? ADN2819 0.1 f nin pin 50 ? tia vref vc c 50 ? 02999-b - 026 f i gur e 2 6 . ADN2819 wi th dc- c o u pl e d inputs v cm = 0.4v min ( dc-coupled) v se = 5mv mi n pin nin v p-p = pin ? nin = 2 v se = 10mv at sensitivity i n put (v) 02999- b- 027 f i gure 27. m i n i m u m allow e d dc- c ou pled inp u t l e v e ls input (v) pin nin v cm = 0.6v ( dc-coupled) v se = 1.2v max v p-p = pin ? nin = 2 v se = 2.4v max 02999- b- 028 f i g u re 28. m a x i mu m a l lowed dc- c ou pled inp u t l e vels
ADN2819 rev. b | page 21 of 24 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 29. 48-lead lead frame chip scale package [lfcsp] 7 mm 7 mm body (cp-48) dimensions shown in millimeters ordering guide model temperature range package description package option ADN2819acp-cml C40c to +85c 48-lead lfcsp cp-48 ADN2819acp-cml-rl C40c to +85c 48-lead lfcsp cp-48 ADN2819acpz-cml 1 C40c to +85c 48-lead lfcsp cp-48 ADN2819acpz-cml-rl 1 C40c to +85c 48-lead lfcsp cp-48 eval-ADN2819-cml evaluation board 1 z = pb free.
ADN2819 rev. b | page 22 of 24 notes
ADN2819 rev. b | page 23 of 24 notes
ADN2819 rev. b | page 24 of 24 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c02999C0 C 5/04(b)

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